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Resumen del manual
tUI is an unlimited interlock, that has no maximum time value. tMLI is a limited time-out that has a defined minimum. tLI is a limited time-out, that has a defined maximum. 2) All timing parameters are measured at the connector of the device to which the parameter applies. For example, the sender shall stop generating STROBE edges tRFS after the negation of DMARDY-. Both STROBE and DMARDY- timing measurements are taken at the connector of the sender. 3) All timing measurement switching points (low to high and high to low) are to be taken at 1.5 V. 5-98 C141-E050-02EN 5.6 Timing 5.6.4.3 Sustained Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: DD (15:0) and DSTROBE are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device. Figure 5.14 Sustained Ultra DMA data in burst C141-E050-02EN 5-99 Interface 5.6.4.4 Host pausing an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Notes: 1) The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY- is negated. 2) If the tSR timing is not satisfied, the host may receive zero, one or two more data words from the device. Figure 5.15 Host pausing an Ultra DMA data in burst 5-100 C141-E050-02EN 5.6 Timing 5.6.4.5 Device terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.16 Device terminating an Ultra DMA data in burst C141-E050-02EN 5-101 Interface 5.6.4.6 Host terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.17 Host terminating an Ultra DMA data in burst 5-102 C141-E050-02EN 5.6 Timing 5.6.4.7 Initiating an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. Figure 5.18 Initiating an Ultra DMA data out burst C141-E050-02EN 5-103 Interface 5.6.4.8 Sustained Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host. Figure 5.19 Sustained Ultra DMA data out burst 5-104 C141-E050-02EN 5.6 Timing 5.6.4.9 Device pausing an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Notes: 1) The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY- is negated. 2) If the tSR timing is not satisfied, the device may receive zero, one or two more data words from the host. Figure 5.20 Device pausing an Ultra DMA data out burst C141-E050-02EN 5-105 Interface 5.6.4.10 Host terminating an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.21 Host terminating an Ultra DMA data out burst 5-106 C141-E050-02EN 5.6 Timing 5.6.4.11 Device terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.22 Device terminating an Ultra DMA data out burst C141-E050-02EN 5-107 Interface 5-108 C141-E050-02EN 5.6.5 Power-on and reset Figure 5.11 shows power-on and reset (hardware and software reset) timing. (1) Only master device is present (2) Master and slave devices are present (2-drives configulation) Figure 5.23 Power on Reset Timing 31 Power-on Reset RESET– PDIAG- negation CHAPTER 6 Operations 6.1 Device Response to the Reset 6.2 Address Translation 6.3 Power Save 6.4 Defect Management 6.5 Read-Ahead Cache 6.6 Write Cache C141-E050-02EN Operations 6.1 Device Response to the Reset This section describes how the PDIAG- and DASP- signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command. 6.1.1 Response to power-on After the master device (device 0) releases its own power-on reset state, the master device shall check a DASP- signal for up to 450 ms to confirm presence of a slave devi...
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