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Resumen del manual
All trademarks are the property of their respective holders. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ADSP-2186 FUNCTIONAL BLOCK DIAGRAM ADSP-2100 BASE SHIFTERMACALU ARITHMETIC UNITS EXTERNAL DATA BUS SERIAL PORTS TIMER INTERNAL SPORT 0 SPORT 1 DMA PORT HOST MODE ARCHITECTURE Six External Interrupts 13 Programmable Flag Pins Provide Flexible System Signaling UART Emulation through Software SPORT Reconfiguration ICE-Port™* Emulator Interface Supports Debugging in Final Systems GENERAL NOTE This data sheet represents production grade specifications for the ADSP-2186 (5 V) processor. This data sheet also contains preliminary (x-grade) specifications for the new ADSP-2186 40 MHz processor. GENERAL DESCRIPTION The ADSP-2186 is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSP-2186 combines the ADSP-2100 family base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities and on-chip program and data memory. The ADSP-2186 integrates 40K bytes of on-chip memory configured as 8K words (24-bit) of program RAM and 8K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable equipment. The ADSP-2186 is available in 100-pin TQFP package. In addition, the ADSP-2186 supports new instructions, which include bit manipulations—bit set, bit clear, bit toggle, bit test— new ALU constants, new multiplication instruction (x squared), One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: Fax: 617/326-8703 © Analog Devices, Inc., 1997 MEMORY PROGRAMMABLE I/O AND FLAGS BYTE DMA CONTROLLER 8K 24 PROGRAM MEMORY 8K 16 DATA MEMORY POWER-DOWN CONTROL PROGRAM SEQUENCERDAG 2DAG 1 DATA ADDRESS GENERATORS PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA DATA MEMORY DATA EXTERNAL DATA BUS EXTERNAL ADDRESS BUS OR FULL MEMORY MODE ADSP-2186 biased rounding, result free ALU operations, I/O memory transfers and global interrupt masking for increased flexibility. Fabricated in a high speed, double metal, low power, CMOS process, the ADSP-2186 operates with a 30 ns instruction cycle time. Every instruction can execute in a single processor cycle. The ADSP-2186’s flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle the ADSP-2186 can: • Generate the next program address • Fetch the next instruction • Perform one or two data moves • Update one or two data address pointers • Perform a computational operation This takes place while the processor continues to: • Receive and transmit data through the two serial ports • Receive and/or transmit data through the internal DMA port • Receive and/or transmit data through the byte DMA port • Decrement timer Development System The ADSP-2100 Family Development Software, a complete set of tools for software and hardware system development, supports the ADSP-2186. The System Builder provides a high level method for defining the architecture of systems under development. The Assembler has an algebraic syntax that is easy to program and debug. The Linker combines object files into an executable file. The Simulator provides an interactive instruction- level simulation with a reconfigurable user interface to display different portions of the hardware environment. A PROM Splitter generates PROM programmer compatible files. The C Compiler, based on the Free Software Foundation’s GNU C Compiler, generates ADSP-2186 assembly source code. The source code debugger allows programs to be corrected in the C environment. The Runtime Library includes over 100 ANSI-standard mathematical and DSP-specific functions. The EZ-KIT Lite is a hardware/software kit offering a complete development environment for the entire ADSP-21xx family: an ADSP-218x based evaluation board with PC monitor software plus Assembler, Linker, Simulator and PROM Splitter software. The ADSP-21xx EZ-KIT Lite is a low cost, easy to use hardware platform on which you can quickly get started with your DSP software design. The EZ-KIT Lite includes the following features: • 33 MHz ADSP-2181 • Full 16-bit Stereo Audio I/O with AD1847 SoundPort®* Codec • RS-232 Interface to PC with Microsoft® Windows 3.1 Control Software • EZ-ICE®* Connector for Emulator Control • DSP Demo Programs The ADSP-218x EZ-ICE®* Emulator aids in the hardware debugging of an ADSP-2186 system. ...