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Resumen del manual
Its 140 MSPS encode rate capability and full power analog bandwidth of 300 MHz supports resolutions up to SXGA (1280 . 1024 at 75 Hz). The AD9883A includes a 140 MHz triple ADC with internal 1.25 V reference, a PLL, and programmable gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and HSYNC and COAST signals. Three-state CMOS outputs may be powered from 2.5 V to 3.3 V. The AD9883A’s on-chip PLL generates a pixel clock from HSYNC and COAST inputs. Pixel clock output frequencies REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its AD9883A FUNCTIONAL BLOCK DIAGRAM RAIN SYNC PROCESSING AND CLOCK GENERATION REF SERIAL REGISTER AND POWER MANAGEMENT AD9883A CLAMP 8A/D CLAMP 8A/D CLAMP 8A/D ROUTA GAIN GOUTA BAIN BOUTA MIDSCV HSYNC DTACK COAST HSOUT CLAMP VSOUT SOGOUT FILT REF BYPASS SCL SDA A0 range from 12 MHz to 140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of HSYNC. A sampling phase adjustment is provided. Data, HSYNC and Clock output phase relationships are maintained. The AD9883A also offers full sync processing for composite sync and sync-on-green applications. A clamp signal is generated internally or may be provided by the user through the CLAMP input pin. This interface is fully programmable via a 2-wire serial interface. Fabricated in an advanced CMOS process, the AD9883A is provided in a space-saving 80-lead LQFP surface mount plastic package and is specified over the 0°C to 70°C temperature range. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2001 AD9883A–SPECIFICATIONS Analog Interface (VD = 3.3 V, VDD = 3.3 V, ADC Clock = Maximum Conversion Rate unless otherwise noted.) Parameter Temp Test Level AD9883AKST-110 Min Typ Max AD9883AKST-140 Min Typ Max Unit RESOLUTION 8 8 Bits DC ACCURACY Differential Nonlinearity 25°C Full I VI ± 0.5 +1.25/–1.0 +1.35/–1.0 ± 0.5 +1.35/–1.0 +1.45/–1.0 LSB LSB Integral Nonlinearity 25°C Full I VI ± 0.5 ± 1.85 ± 2.0 ± 0.5 ± 2.0 ± 2.3 LSB LSB No Missing Codes Full VI Guaranteed Guaranteed ANALOG INPUT Input Voltage Range Minimum Full VI 0.5 0.5 V p-p Maximum Full VI 1.0 1.0 V p-p Gain Tempco 25°C V 100 100 ppm/°C Input Bias Current 25°C IV 1 1 .A Full IV 1 1 .A Input Offset Voltage Full VI 7 50 7 70 mV Input Full-Scale Matching Full VI 1.5 6.0 1.5 8.0 % FS Offset Adjustment Range Full VI 46 49 52 46 49 52 % FS REFERENCE OUTPUT Output Voltage Temperature Coefficient Full Full VI V 1.20 1.25 1.32 ± 50 1.20 1.25 1.32 ± 50 V ppm/°C SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 110 140 MSPS Minimum Conversion Rate Full IV 10 10 MSPS Data to Clock Skew Full IV –0.5 +2.0 –0.5 +2.0 ns tBUFF Full VI 4.7 4.7 .s tSTAH Full VI 4.0 4.0 .s tDHO Full VI 0 0 .s tDAL Full VI 4.7 4.7 .s tDAH Full VI 4.0 4.0 .s tDSU Full VI 250 250 .s tSTASU Full VI 4.7 4.7 .s tSTOSU Full VI 4.0 4.0 .s HSYNC Input Frequency Full IV 15 110 15 110 kHz Maximum PLL Clock Rate Full VI 110 140 MHz Minimum PLL Clock Rate Full IV 12 12 MHz PLL Jitter 25°C IV 400 7001 400 7001 ps p-p Full IV 10001 10001 ps p-p Sampling Phase Tempco Full IV 15 15 ps/°C DIGITAL INPUTS Input Voltage, High (VIH) Full VI 2.5 2.5 V Input Voltage, Low (VIL) Full VI 0.8 0.8 V Input Voltage, High (VIH) Full V –1.0 –1.0 .A Input Voltage, Low (VIL) Full V +1.0 +1.0 .A Input Capacitance 25°C V 3 3 pF –2– REV. 0 AD9883A Parameter Temp Test Level AD9883AKST-110Min Typ Max AD9883AKST-140 Min Typ Max Unit DIGITAL OUTPUTS Output Voltage, High (VOH) Output Voltage, Low (VOL) Duty Cycle DATACK Output CodingFull Full Full VI VI IV VD – 0.1 0.1 45 50 55 BinaryVD – 0.1 0.1 45 50 55 Binary V V % POWER SUPPLY VD Supply Voltage Full IV 3.0 3.3 3.6 3.15 3.3 3.6 V VDD Supply Voltage Full IV 2.2 3.3 3.6 2.2 3.3 3.6 V PVD Supply Voltage Full IV 3.0 3.3 3.6 3.0 3.3 3.6 V ID Supply Current (VD) 25°C V 132 180 mA IDD Supply Current (VDD)2 25°C V 19 26 mA IPVD Supply Current (PVD) 25°C V 8 11 mA Total Power Dissipation Full VI 525 650 650 800 mW Power-Down Supply Current Full VI 5 10 5 10 mA Power-Down Dissipation Full VI 16.5 33 16.5 33 mW DYNAMIC PERFORMANCE Analog Bandwidth, Full Power 25°C V 300 300 MHz Transient Response 25°C V 2 2 ns Overvoltage Recovery Time 25°C V 1.5 1.5 ns Signal-to-Noise Ratio (SNR) 25°C V 44 43 dB (Without Harmonics) fIN = 40.7 MHz Full V 43 42 dB Crosstalk Full V 55 55 dBc THERMAL CHARACTERISTICS .JC Junction-to-Case Thermal Resistance .JA Junction-to-Ambient V 16 16 °C/W Thermal Resistance V 35 35 °C/W NOTES 1VCO Range = 10, Charge Pump Current = 110, PLL Divider = 1693. 2DATACK Load = 15 pF...