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See Figure 3, "AMD Athlon™ XP Processor Model 10 Power Management States" on page 9. 2. The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the worst case corner of the process and are not representative of the typical Stop Grant current that is currently about one-third of the maximum specified current. 3. These currents occur when the AMD Athlon™ system bus is disconnected and has a low power ratio of 1/8 for Stop Grant disconnect and a low power ratio of 1/8 Halt disconnect applied to the core clock grid of the processor as dictated by a value of 2003_1223h programmed into the Clock Control (CLK_Ctl) MSR. For more information, refer to the AMD Athlon™ and AMD Duron™ Processors BIOS, Software, and Debug Developers Guide, order# 21656. 4. The Stop Grant current consumption is characterized at 50°C and not tested. 5. Thermal design power represents the maximum sustained power dissipated while executing publicly-available software or instruction sequences under normal system operation at nominal VCC_CORE . Thermal solutions must monitor the temperature of the processor to prevent the processor from exceeding its maximum die temperature. Chapter 6 Advanced 333 Front-Side Bus AMD Athlon™ XP Processor Model 10 Specifications Preliminary Information AMD Athlon™ XP Processor Model 10 Data Sheet 26237C—May 2003 Advanced 333 FSB AMD Athlon™ XP Processor Model 10 SYSCLK and SYSCLK# AC Characteristics Table 2 shows the SYSCLK/SYSCLK# differential clock AC characteristics of this processor. Table 2. Advanced 333 FSB SYSCLK and SYSCLK# AC Characteristics Symbol Parameter Description Minimum Maximum Units Notes Clock Frequency 50 166 MHz 1 Duty Cycle 30% 70% t1 Period 6 ns 2, 3 t2 High Time 1.0 ns t3 Low Time 1.0 ns t4 Fall Time 2 ns t5 Rise Time 2 ns Period Stability ± 300 ps Notes: 1. The AMD Athlon™ system bus operates at twice this clock frequency. 2. Circuitry driving the AMD Athlon system bus clock inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the PLL to track the jitter. The –20dB attenuation point, as measured into a 20or 30-pF load must be less than 500 kHz. 3. Circuitry driving the AMD Athlon system bus clock inputs may purposely alter the AMD Athlon system bus clock frequency (spread spectrum clock generators). In no cases can the AMD Athlon system bus period violate the minimum specification above. AMD Athlon system bus clock inputs can vary from 100% of the specified frequency to 99% of the specified frequency at a maximum rate of 100 kHz. Figure 8 shows a sample waveform of the SYSCLK signal. t5 VCROSS t2 t3 t4 t1 VThreshold-AC Figure 8. SYSCLK Waveform 22 Advanced 333 Front-Side Bus AMD Athlon™ XP Processor Model 10 Specifications Chapter 6 Preliminary Information 26237C—May 2003 AMD Athlon™ XP Processor Model 10 Data Sheet Advanced 333 FSB AMD Athlon™ System Bus AC Characteristics The AC characteristics of the AMD Athlon system bus of this processor are shown in Table 3. The parameters are grouped based on the source or destination of the signals involved. Table 3. Advanced 333 FSB AMD Athlon™ System Bus AC Characteristics Group Symbol Parameter Min Max Units Notes All Signals TRISE Output Rise Slew Rate 1 3 V/ns 1 TFALL Output Fall Slew Rate 1 3 V/ns 1 Forward Clocks TSKEW-DIFFEDGE Output skew with respect to a different clock edge – 770 ps 2 TSU Input Data Setup Time 300 ps 3 THD Input Data Hold Time 300 ps 3 CIN Capacitance on input clocks 4 25 pF COUT Capacitance on output clocks 4 12 pF Sync TVAL RSTCLK to Output Valid 800 2000 ps 4, 5 TSU Setup to RSTCLK 500 ps 4, 6 THD Hold from RSTCLK 500 ps 4, 6 Notes: 1. Rise and fall time ranges are guidelines over which the I/O has been characterized. 2. TSKEW-DIFFEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and its forward clock, as measured at the package, with respect to different clock edges. 3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock. 4. The synchronous signals include PROCRDY, CONNECT, and CLKFWDRST. 5. TVAL is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF. 6. TSU is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. THD is hold of CONNECT/CLKFWDRST from rising edge of RSTCLK. Chapter 6 Advanced 333 Front-Side Bus AMD Athlon™ XP Processor Model 10 Specifications Preliminary Information AMD Athlon™ XP Processor Model 10 Data Sheet 26237C—May 2003 Advanced 333 FSB AMD Athlon™ System Bus DC Characteristics Table 4 shows the DC characteristics of the AMD Athlon system bus for this processor. Table 4. Advanced 333 FSB AMD Athlon™ System Bus DC Characteristics Symbol Parameter Condition Min Max Units Notes VREF DC Input Reference Voltage (0.5 x VCC_CORE) –50 (0.5 x VCC_CORE) +50 mV 1 IVREF_LEAK_P VREF Tristate Leakage Pullup VIN = VREF Nominal –100 .A IVREF_LEAK_N VREF Tristate Leakage Pulldown VIN = VREF Nominal 100 .A VIH Input High Voltage VREF +200 VCC_CORE +...

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