Votos - , Puntuación media:
(
)
)
Fabricar: AMD
Tamaño del archivo: 2.38 mb
Nombre del archivo: 8805a92e-5b41-4395-a9d8-9d8162d03eed.pdf
Idioma del manual:
El documento se está cargando, por favor, espere
 |
El documento se está cargando, por favor, espere
Resumen del manual
0: No. 1: Yes. To enable SMI generation, set F0 Index 83h[7] = 1. AMD Geode™ SC3200 Processor Data Book 32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description 3 Keyboard/Mouse Access Trap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to the keyboard or mouse. 0: No. 1: Yes. To enable SMI generation, set F0 Index 82h[3] = 1. 2 Parallel/Serial Access Trap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to either the serial or parallel ports. 0: No. 1: Yes. To enable SMI generation, set F0 Index 82h[2] =1. 1 Floppy Disk Access Trap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to the floppy disk. 0: No. 1: Yes. To enable SMI generation, set F0 Index 82h[1] = 1. 0 Primary Hard Disk Access Trap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to the primary hard disk. 0: No. 1: Yes. To enable SMI generation, set F0 Index 82h[0] = 1. Index F7h Second Level PME/SMI Status Register 4 (RC) Reset Value: 00h The bits in this register contain second level status reporting. Top level status is reported in F1BAR0+I/O Offset 00h/02h[0]. Reading this register clears the status at both the second and top levels except for bit 7 which has a third level of status reporting at F0BAR0+I/O 0Ch/1Ch. A read-only “Mirror” version of this register exists at F0 Index 87h. If the value of the register must be read without clearing the SMI source (and consequently de-asserting SMI), F0 Index 87h can be read instead. 7 GPIO Event SMI Status (Read Only, Read does not Clear). Indicates whether or not an SMI was caused by a transition of any of the GPIOs (GPIO47-GPIO32 and GPIO15-GPIO0). 0: No. 1: Yes. To enable SMI generation, set F1BAR1+I/O Offset 0Ch[0] = 0. F0BAR0+I/O Offset 08h/18h selects which GPIOs are enabled to generate a PME and setting F1BAR1+I/O Offset 0Ch[0] = 0 enables the PME to generate an SMI. In addition, the selected GPIO must be enabled as an input (F0BAR0+I/O Offset 20h and 24h). The next level (third level) of SMI status is at F0BAR0+I/O 0Ch/1Ch. 6 Thermal Override SMI Status. Indicates whether or not an SMI was caused by an assertion of the THRM#. 0: No. 1: Yes. To enable SMI generation set F0 Index 83h[4] = 1. 5:4 Reserved. Read as 0. 3 SIO PWUREQ SMI Status. Indicates whether or not an SMI was caused by a power-up event from the SIO. 0: No. 1: Yes. A power-up event is defined as any of the following events/activities: —RI2# —SDATA_IN2 — IRRX1 (CEIR) To enable SMI generation, set F1BAR1+I/O Offset 0Ch[0] = 0. AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 32581C Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description 2 Codec SDATA_IN SMI Status. Indicates whether or not an SMI was caused by AC97 Codec producing a positive edge on SDATA_IN. 0: No. 1: Yes. To enable SMI generation, set F0 Index 80h[5] = 1. 1 RTC Alarm (IRQ8#) SMI Status. Indicates whether or not an SMI was caused by an RTC interrupt. 0: No. 1: Yes. This SMI event can only occur while in 3V Suspend and an RTC interrupt occurs and F1BAR1+I/O Offset 0Ch[0] = 0. 0 ACPI Timer SMI Status. Indicates whether or not an SMI was caused by an ACPI Timer (F1BAR0+I/O Offset 1Ch or F1BAR1+I/O Offset 1Ch) MSB toggle. 0: No. 1: Yes. To enable SMI generation, set F0 Index 83h[5] = 1. Index F8h-FFh Reserved Reset Value: 00h AMD Geode™ SC3200 Processor Data Book 32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 6.4.1.1 GPIO Support Registers F0 Index 10h, Base Address Register 0 (F0BAR0) points to ration registers are located. Table 6-29 gives the bit formats the base address of where the GPIO runtime and configu-of I/O mapped registers accessed through F0BAR0. Table 6-30. F0BAR0+I/O Offset: GPIO Configuration Registers Bit Description Offset 00h-03h GPDO0 — GPIO Data Out 0 Register (R/W) Reset Value: FFFFFFFFh 31:0 GPIO Data Out. Bits [31:0] of this register correspond to GPIO31-GPIO0 signals, respectively. The value of each bit determines the value driven on the corresponding GPIO signal when its output buffer is enabled. Writing to the bit latches the written data unless the bit is locked by the GPIO Configuration register Lock bit (F0BAR0+I/O Offset 24h[3]). Reading the bit returns the value, regardless of the signal value and configuration. 0: Corresponding GPIO signal is driven to low when output enabled. 1: Corresponding GPIO signal is driven or released to high (according to buffer type and static pull-up selection) when output is enabled. Offset 04h-07h GPDI0 — GPIO Data In 0 Register (RO) Reset Value: FFFFFFFFh 31:0 GPIO Data In. Bits [31:0] of this register correspond to GPIO31-GPIO0 signals, respectively. Reading each bit returns the value of the corresponding GPIO signal, rega...