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Resumen del manual
Device Comparison ¦ Meets Rambus® Extended Data Rate (XDR™) clocking requirements ¦ 25 ps typical cycle-to-cycle jitter . –135 dBc/Hz typical phase noise at 20 MHz offset ¦ 100 or 133 MHz differential clock input CY24271 CY24272 SDA hold time = 300 ns (SMBus compliant) SDA hold time = 0 ns (I2C compliant) RRC = 200. typical (Rambus standard drive) RRC = 295. minimum (Reduced output drive) ¦ 300–667 MHz high speed clock support ¦ Quad (open drain) differential output drivers ¦ Supports frequency multipliers: 3, 4, 5, 6, 9/2 and 15/4 ¦ Spread Aware™ ¦ 2.5V operation ¦ 28-pin TSSOP package CLK0 CLK0B CLK1 CLK1B CLK2 CLK2B CLK3 CLK3B REFCLK,REFCLKB SCL SDA ID0 ID1 EN RegB EN RegC EN RegD EN RegA PLL Bypass MUX /BYPASS EN Logic Block Diagram Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 001-42414 Rev. ** Revised November 9, 2007 [+] Feedback CY24272 Pinouts Figure 1. Pin Diagram - 28 Pin TSSOP 1 VDD VDDP 28 CLK0 VSSP 2 27 ISET CLK0B 3 26 VSS VSS 4 25 CLK1 REFCLK 5 24 CLK1B REFCLKB 6 23 VDDC VDD 7 22 VSSC VSS 8 21 SCL CLK2 9 20 CLK2B SDA 10 19 VSS EN11 18 CLK3 ID0 12 17 CLK3B ID1 13 16 VDD /BYPASS 14 15 Table 2. Pin Definition - 28 Pin TSSOP CY24272 Pin No. Name IO Description 1 VDDP PWR 2.5V power supply for phased lock loop (PLL) 2 VSSP GND Ground 3 ISET I Set clock driver current (external resistor) 4 VSS GND Ground 5 REFCLK I Reference clock input (connect to clock source) 6 REFCLKB I Complement of reference clock (connect to clock source) 7 VDDC PWR 2.5V power supply for core 8 VSSC GND Ground 9 SCL I SMBus clock (connect to SMBus) 10 SDA I SMBus data (connect to SMBus) 11 EN I Output Enable (CMOS signal) 12 ID0 I Device ID (CMOS signal) 13 ID1 I Device ID (CMOS signal) 14 /BYPASS I REFCLK bypassing PLL (CMOS signal) 15 VDD PWR Power supply for outputs 16 CLK3B O Complement clock output 17 CLK3 O Clock output 18 VSS GND Ground 19 CLK2B O Complement clock output 20 CLK2 O Clock output 21 VSS GND Ground 22 VDD PWR Power supply for outputs 23 CLK1B O Complement clock output 24 CLK1 O Clock output 25 VSS GND Ground 26 CLK0B O Complement clock output 27 CLK0 O Clock output 28 VDD PWR Power supply for outputs Document Number: 001-42414 Rev. ** Page 2 of 13 [+] Feedback CY24272 PLL Multiplier Table 3 shows the frequency multipliers in the PLL, selectable by programming the SMBus registers MULT0, MULT1, and MULT2. Default multiplier at power up is 4. Table 3. PLL Multiplier Selection Register Frequency Multiplier Output Frequency (MHz) MULT2 MULT1 MULT0 REFCLK = 100 MHz[1], REFSEL = 0 REFCLK = 133 MHz[1], REFSEL = 1 0 0 0 3 300 400 0 0 1 4 400[2] – 0 1 0 5 500 667 0 1 1 6 600 – 1 0 0 Reserved – – 1 0 1 9/2 450 600 1 1 0 Reserved – – 1 1 1 15/4 375 500 Input Clock Signal The XCG receives either a differential (REFCLK/REFCLKB) or a single-ended reference clocking input (REFCLK). When the reference input clock is from a different clock source, it must meet the voltage levels and timing requirements listed in DC Operating Conditions on page 7 and AC Operating Conditions on page 8. For a single-ended clock input, an external voltage divider and a supply voltage, as shown in Figure 2 on page 6, provide a reference voltage VTH at the REFCLKB pin. This determines the proper trip point of REFCLK. For the range of VTH specified in DC Operating Conditions on page 7, the outputs also meet the DC and AC Operating Conditions tables. Table 4. SMBus Device Addresses for CY24272 Modes of Operation The modes of operation are determined by the logic signals applied to the EN and /BYPASS pins and the values in the five SMBus Registers: RegTest, RegA, RegB, RegC, and RegD. Table 5 on page 4 shows selection from one to all four of the outputs, the Outputs Disabled Mode (EN = low), and Bypass Mode (EN = high, /BYPASS = low). There is an option reserved for vendor test. Disabled outputs are set to High Z. At power up, the SMBus registers default to the last entry in Table 6 on page 5. The value at RegTest is 0. The values at RegA, RegB, RegC, and RegD are all ‘1’. Thus, all outputs are controlled by the logic applied to EN and /BYPASS. XCG Hex Address 8-bit SMBus Device Address Including Operation Device Operation Five Most Significant Bits ID1 ID0 WR# / RD 0 Write D8 1 1 0 1 1 0 0 0 Read D9 1 1 Write DA 0 1 0 Read DB 1 2 Write DC 1 0 0 Read DD 1 3 Write DE 1 1 0 Read DF 1 Notes 1. Output frequencies shown in Table 3 are based on nominal input frequencies of 100 MHz and 133.3 MHz. The PLL multipliers are applicable to spread spectrummodulated input clock with maximum and minimum input cycle time. The REFSEL bit in SMBus 81h is set correctly as shown. 2. Default PLL multiplier at power up. Document Number: 001-42414 Rev. ** Page 3 of 13 [+] Feedback CY24272 Table 5. Modes of Operation for CY24272 EN /BYPASS RegTest RegA RegB RegC RegD CLK0/CLK0B CLK1/CLK1B CLK2/CLK2B CLK3/CLK3B L X X X X X X High Z High Z High Z High Z H X 1 X X X X Reserved for Vendor Test H L 0 X X X X REF...
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