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Max Unit VIH Input HIGH Voltage VREF + 0.2 – VDDQ + 0.24 V VIL Input LOW Voltage –0.24 – VREF – 0.2 V Notes 15. Power up: assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 16. Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175. < RQ < 350.. 17. Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175. < RQ < 350.. 18. VREF (min) = 0.68V or 0.46VDDQ, whichever is larger. VREF (max) = 0.95V or 0.54VDDQ, whichever is smaller. 19. The operation current is calculated with 50% read cycle and 50% write cycle. Document Number: 001-06348 Rev. *D Page 20 of 27 [+] Feedback [+] Feedback[+] Feedback CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 \ Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions Max Unit CIN Input Capacitance TA = 25°C, f = 1 MHz, 5 pF CCLK Clock Input Capacitance VDD = 1.8V VDDQ = 1.5V 4 pF CO Output Capacitance 5 pF Thermal Resistance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions 165 FBGA Package Unit .JA Thermal Resistance (Junction to Ambient) Test conditions follow standard test methods and procedures for measuring thermal impedance, per 16.25 °C/W .JC Thermal Resistance (Junction to Case) EIA/JESD51. 2.91 °C/W AC Test Loads and Waveforms Figure 4. AC Test Loads and Waveforms VREF = 0.75V 0.75V VREF OUTPUT Device Under Test OUTPUT 0.75VVREF ZQ RQ = 250. R = 50. [20] ALL INPUT PULSES Z0= 50. 1.25V 0.75V Device RL= 50. Under Test 5pF 0.25V VREF = 0.75V Slew Rate = 2 V/ns ZQ RQ = 250. INCLUDING JIG AND (a) (b) SCOPE Note 20. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, VREF = 0.75V, RQ = 250., VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms. Document Number: 001-06348 Rev. *D Page 21 of 27 [+] Feedback [+] Feedback[+] Feedback CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Switching Characteristics Over the Operating Range [20, 21] Cypress Parameter Consortium Parameter Description 375 MHz 333 MHz 300 MHz Unit Min Max Min Max Min Max tPOWER VDD(Typical) to the first Access[22] 1 – 1 – 1 – ms tCYC tKHKH K Clock Cycle Time 2.66 8.4 3.0 8.4 3.3 8.4 ns tKH tKHKL Input Clock (K/K) HIGH 0.4 – 0.4 – 0.4 – tCYC tKL tKLKH Input Clock (K/K) LOW 0.4 – 0.4 – 0.4 – tCYC tKHKH tKHKH K Clock Rise to K Clock Rise (rising edge to rising edge) 1.13 – 1.28 – 1.40 – ns Setup Times tSA tAVKH Address Setup to K Clock Rise 0.4 – 0.4 – 0.4 – ns tSC tIVKH Control Setup to K Clock Rise (LD, R/W) 0.4 – 0.4 – 0.4 – ns tSCDDR tIVKH Double Data Rate Control Setup to Clock (K, K) Rise (BWS0, BWS1, BWS2, BWS3) 0.28 – 0.28 – 0.28 – ns tSD tDVKH D[X:0] Setup to Clock (K/K) Rise 0.28 – 0.28 – 0.28 – ns Hold Times tHA tKHAX Address Hold after K Clock Rise 0.4 – 0.4 – 0.4 – ns tHC tKHIX Control Hold after K Clock Rise (LD, R/W) 0.4 – 0.4 – 0.4 – ns tHCDDR tKHIX Double Data Rate Control Hold after Clock (K/K) Rise (BWS0, BWS1, BWS2, BWS3) 0.28 – 0.28 – 0.28 – ns tHD tKHDX D[X:0] Hold after Clock (K/K) Rise 0.28 – 0.28 – 0.28 – ns Output Times tCO tCHQV K/K Clock Rise to Data Valid – 0.45 – 0.45 – 0.45 ns tDOH tCHQX Data Output Hold after K/K Clock Rise (Active to Active) –0.45 – –0.45 – –0.45 – ns tCCQO tCHCQV K/K Clock Rise to Echo Clock Valid – 0.45 – 0.45 – 0.45 ns tCQOH tCHCQX Echo Clock Hold after K/K Clock Rise –0.45 – –0.45 – –0.45 – ns tCQD tCQHQV Echo Clock High to Data Valid – 0.2 – 0.2 – 0.2 ns tCQDOH tCQHQX Echo Clock High to Data Invalid –0.2 – –0.2 – –0.2 – ns tCQH tCQHCQL Output Clock (CQ/CQ) HIGH[23] 0.88 – 1.03 – 1.15 – ns tCQHCQH tCQHCQH CQ Clock Rise to CQ Clock Rise[23] (rising edge to rising edge) 0.88 – 1.03 – 1.15 – ns tCHZ tCHQZ Clock (K/K) Rise to High-Z (Active to High-Z)[24, 25] – 0.45 – 0.45 – 0.45 ns tCLZ tCHQX1 Clock (K/K) Rise to Low-Z[24, 25] –0.45 – –0.45 – –0.45 – ns tQVLD tCQHQVLD Echo Clock High to QVLD Valid[26] –0.20 0.20 –0.20 0.20 –0.20 0.20 ns DLL Timing tKC Var tKC Var Clock Phase Jitter – 0.20 – 0.20 – 0.20 ns tKC lock tKC lock DLL Lock Time (K) 2048 – 2048 – 2048 – Cycles tKC Reset tKC Reset K Static to DLL Reset[27] 30 – 30 – 30 – ns Notes 21. When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timing of the frequency range in which it is being operated and outputs data with the output timing of that frequency range. 22. This part has an internal voltage regulator; tPOWER is the time that the power must be supplied above VDD minimum initially before a read or write operation can be initiated. 23. These parameters are extrapolated from the input timing parameters (tKHKH - 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (tKC Var) is alreadyincluded in the tKHKH). These ...

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