Votos - 4, Puntuación media: 3.8
(
)
)
|
Resumen del manual
7:4 INTB# (Ball C26) Target Interrupt. 0000: Disable 0100: IRQ4 1000: Reserved 1100: IRQ12 0001: IRQ1 0101: IRQ5 1001: IRQ9 1101: Reserved 0010: Reserved 0110: IRQ6 1010: IRQ10 1110: IRQ14 0011: IRQ3 0111: IRQ7 1011: IRQ11 1111: IRQ15 3:0 INTA# (Ball D26) Target Interrupt. 0000: Disable 0100: IRQ4 1000: Reserved 1100: IRQ12 0001: IRQ1 0101: IRQ5 1001: IRQ9 1101: Reserved 0010: Reserved 0110: IRQ6 1010: IRQ10 1110: IRQ14 0011: IRQ3 0111: IRQ7 1011: IRQ11 1111: IRQ15 Index 5Dh PCI Interrupt Steering Register 2 (R/W) Reset Value: 00h Indicates target interrupts for signals INTD# and INTC#. Note that INTD# is muxed with IDE_DATA7 (selection made via PMR[24]) and INTC# is muxed with GPIO19+IOCHRDY (selection made via PMR[9,4]). See Table 4-2 on page 72 for PMR bit descriptions. Note: The target interrupt must first be configured as level sensitive via I/O Ports 4D0h and 4D1h in order to maintain PCI interrupt compatibility. 7:4 INTD# (Ball AA2) Target Interrupt. 0000: Disable 0100: IRQ4 1000: Reserved 1100: IRQ12 0001: IRQ1 0101: IRQ5 1001: IRQ9 1101: Reserved 0010: Reserved 0110: IRQ6 1010: IRQ10 1110: IRQ14 0011: IRQ3 0111: IRQ7 1011: IRQ11 1111: IRQ15 3:0 INTC# (Ball C9) Target Interrupt. 0000: Disable 0100: IRQ4 1000: Reserved 1100: IRQ12 0001: IRQ1 0101: IRQ5 1001: IRQ9 1101: Reserved 0010: Reserved 0110: IRQ6 1010: IRQ10 1110: IRQ14 0011: IRQ3 0111: IRQ7 1011: IRQ11 1111: IRQ15 Index 5Eh-5Fh Reserved Reset Value: 00h AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 60h-63h ACPI Control Register (R/W) Reset Value: 00000000h 31:8 Reserved. Must be set to 0. 7 SUSP_3V Shut Down PLL5. Allow internal SUSP_3V to shut down PLL5. 0: Clock generator is stopped when internal SUSP_3V is active. 1: Clock generator continues working when internal SUSP_3V is active. 6 SUSP_3V Shut Down PLL4. Allow internal SUSP_3V to shut down PLL4 0: Clock generator is stopped when internal SUSP_3V is active. 1: Clock generator continues working when internal SUSP_3V is active. 5 SUSP_3V Shut Down PLL3. Allow internal SUSP_3V to shut down PLL3. 0: Clock generator is stopped when internal SUSP_3V is active. 1: Clock generator continues working when internal SUSP_3V is active. 4 SUSP_3V Shut Down PLL2. Allow internal SUSP_3V to shut down PLL2. 0: Clock generator is stopped when internal SUSP_3V is active. 1: Clock generator continues working when internal SUSP_3V is active. 3 SUSP_3V Shut Down PLL6. Allow internal SUSP_3V to shut down PLL6. 0: Clock generator is stopped when internal SUSP_3V is active. 1: Clock generator continues working when internal SUSP_3V is active. 2 ACPI C3 SUSP_3V Enable. Allow internal SUSP_3V to be active during C3 state. 0: Disable. 1: Enable. 1 ACPI SL1 SUSP_3V Enable. Allow internal SUSP_3V to be active during SL1 sleep state. 0: Disable. 1: Enable. 0 ACPI C3 Support Enable. Allow support of C3 states. 0: Disable. 1: Enable. Index 64h-6Bh Reserved Reset Value: 00h Index 6Ch-6Fh ROM Mask Register (R/W) Reset Value: 0000FFF0h Note: Register must be read/written as a DWORD. 31:16 Reserved. Must be written to 0. 15:8 Reserved. Must be written to FFh. 7:4 ROM Size. If F0 Index 52h[2] = 1: 0000: 16 MB = FF000000h-FFFFFFFFh 1110: 2 MB = FFE00000h-FFFFFFFFh 1000: 8 MB = FF800000h-FFFFFFFFh 1111: 1 MB = FFF00000h-FFFFFFFFh 1100: 4 MB = FFC00000h-FFFFFFFFh All other settings for these bits are reserved. 3:0 Reserved. Must be written to 0. Index 70h-71h IOCS1# Base Address Register (R/W) Reset Value: 0000h 15:0 I/O Chip Select 1 Base Address. This 16-bit value represents the I/O base address used to enable assertion of IOCS1# (ball D10 or N30 - see PMR[23] in Table 4-2 on page 72). This register is used in conjunction with F0 Index 72h (IOCS1# Control register). Index 72h IOCS1# Control Register (R/W) Reset Value: 00h This register is used in conjunction with F0 Index 70h (IOCS1# Base Address register). 7 I/O Chip Select 1 Positive Decode (IOCS1#). 0: Disable. 1: Enable. AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 32579B Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description 6 Writes Result in Chip Select. When this bit is set to 1, writes to configured I/O address (base address configured in F0 Index 70h; range configured in bits [4:0]) cause IOCS1# to be asserted. 0: Disable. 1: Enable. 5 Reads Result in Chip Select. When this bit is set to 1, reads from configured I/O address (base address configured in F0 Index 70h; range configured in bits [4:0]) cause IOCS1# to be asserted. 0: Disable. 1: Enable. 4:0 IOCS1# I/O Address Range. This 5-bit field is used to select the range of IOCS1#. 00000: 1 Byte 01111: 16 Bytes 00001: 2 Bytes 11111: 32 Bytes 00011: 4 Bytes All other combinations are reserved. 00111: 8 Bytes Index...
Otros modelos de este manual:Accesorios para el ordenador - Geode SC1200 (2.5 mb)