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Once this flag bit's value is "1", its value is retained until a "0" is written to it. . For details, see "8.3. Fixed-cycle Timer Interrupt Function". 3) AF (Alarm Flag) bit If set to "0" beforehand, this flag bit's value changes from "0" to 1" when an alarm interrupt event has occurred. Once this flag bit's value is "1", its value is retained until a "0" is written to it. . For details, see "8.5. Alarm Interrupt Function". 4) VLF (Voltage Low Flag) bit This flag bit indicates the retained status of clock operations or internal data. Its value changes from "0" to "1" when data loss occurs, such as due to a supply voltage drop. Once this flag bit's value is "1", its value is retained until a "0" is written to it. This bit's value is "1" after powering up from 0 V. VLF Data Description Write 0 The VLF bit is cleared to zero to prepare for the next status detection. 1 This bit is invalid after a "1" has been written to it. Read 0 Data loss is not detected. 1 Data loss is detected. All registers must be initialized. (This setting is retained until a "zero" is written to this bit.) Page - 9 MQ372-02 RX -8581 SA /JE/NB 8.2.4. Extension register (Reg-D) bit 0 D (Default) (0) (.) (.) TE (.) • (0) (0) (.) TSEL0 (.) .1) The default value is the value that is read (or is set internally) after powering up from 0 V. .2) "o" indicates write-protected bits. A zero is always read from these bits. .3) "." indicates a default value is undefined. • This register is used to specify the target for the alarm function or time update interrupt function and to select or set operations such as fixed-cycle timer operations. 1) TEST bit This is the manufacturer's test bit. Its value should always be "0". Be careful to avoid writing a "1" to this bit when writing to other bits. . If a "1" is inadvertently written to this TEST bit, there is a safety function where by this bit will be automatically cleared to zero when a STOP condition or Repeated START condition is received or when the 0.95-second bus timeout function operates. TEST Data Description Write/Read 0 Normal operation mode . Default 1 Setting prohibited (manufacturer's test bit) 2) WADA (Week Alarm/Day Alarm) bit This bit is used to specify either WEEK or DAY as the target of the alarm interrupt function. Writing a "1" to this bit specifies DAY as the comparison object for the alarm interrupt function. Writing a "0" to this bit specifies WEEK as the comparison object for the alarm interrupt function. . For details, see "8.5. Alarm Interrupt Function". 3) USEL (Update Interrupt Select) bit This bit is used to specify either "second update" or "minute update" as the update generation timing of the time update interrupt function. Writing a "1" to this bit specifies the internal clock's "minute update" (once per minute) operation as the timing by which time update interrupts are generated. Writing a "0" to this bit specifies the internal clock's "second update" (once per second) operation as the timing by which time update interrupts are generated. . For details, see "8.4. Time Update Interrupt Function". 4) TE (Timer Enable) bit This bit controls the start/stop setting for the fixed-cycle timer interrupt function. Writing a "1" to this bit specifies starting of the fixed-cycle timer interrupt function (a countdown starts from a preset value). Writing a "0" to this bit specifies stopping of the fixed-cycle timer interrupt function. . For details, see "8.3. Fixed-cycle Timer Interrupt Function". 5) TSEL0,1 (Timer Select 0, 1) bits The combination of these two bits is used to set the countdown period (source clock) for the fixed-cycle timer interrupt function (four settings can be made). TSEL0,1 TSEL1 (bit 1) TSEL0 (bit 0) Source clock 0 0 4096 Hz /Once per 244.14 .s Write/Read 0 1 64 Hz / Once per 15.625 ms 1 0 "Second" update /Once per second 1 1 "Minute" update /Once per minute . For details, see "8.3. Fixed-cycle Timer Interrupt Function". 8.2.5. RAM register (Reg - 7) bit 0 • • This RAM register is read/write accessible for any data in the range from 00 h to FF h. Page - 10 MQ372-02 RX -8581 SA /JE/NB 8.2.6. Clock counter (Reg - 0 . 2) bit 0 SEC 1 MIN 1 HOUR • 1 .) "o" indicates write-protected bits. A zero is always read from these bits. • The clock counter counts seconds, minutes, and hours. • The data format is BCD format. For example, when the "seconds" register value is "0101 1001" it indicates 59 seconds. . Note with caution that writing non-existent time data may interfere with normal operation of the clock counter. 1) Second counter bit 0 SEC 1 • This second counter counts from "00" to "01," "02," and up to 59 seconds, after which it starts again from 00 seconds. • When data was written to seconds counter, the internal divider is reset from 2048Hz to 1Hz. 2) Minute counter bit 0 MIN 1 • This minute counter counts from "00" to "01," "02," and up to 59 minutes, after which it starts again from 00 minutes. 3) Hour counter bit 0 HOUR • 1 • This hour counter counts from "00...

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