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Resumen del manual
Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. The Intel® 440GX AGPset may contain design defects or errors which may cause the products to deviate from published specifications. Current characterized errata are available on request. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by: calling 1-800-548-4725 or by visiting Intel's website at Copyright © Intel Corporation, 1999 *Third-party brands and names are the property of their respective owners. Intel® 440GX AGPset Design Guide Contents 1 Introduction ................................................................................................................1-1 1.1 About This Design Guide..............................................................................1-1 1.2 References....................................................................................................1-2 1.3 Intel® Pentium® II Processor / Intel® 440GX AGPset Overview ...................1-3 1.3.1 Intel® Pentium® II Processor............................................................1-3 1.3.2 Intel® 440GX AGPset ......................................................................1-4 1.3.2.1 System Bus Interface......................................................1-5 1.3.2.2 DRAM Interface ..............................................................1-5 1.3.2.3 Accelerated Graphics Port Interface...............................1-5 1.3.2.4 PCI Interface...................................................................1-6 1.3.2.5 System Clocking.............................................................1-6 1.3.3 PCI-to-ISA/IDE Xcelerator (PIIX4E).................................................1-6 1.3.3.1 Instrumentation...............................................................1-7 1.3.3.2 Remote Service Boot......................................................1-7 1.3.3.3 Remote Wake-Up ...........................................................1-8 1.3.3.4 Power Management........................................................1-8 1.4 Design Recommendations............................................................................1-8 1.4.1 Voltage Definitions...........................................................................1-8 1.4.2 General Design Recommendations .................................................1-9 1.4.3 Transitioning from Intel “ 440BX AGPset to Intel “ 440GX AGPset Design ................................................................................1-9 2 Motherboard Layout and Routing Guidelines ............................................................2-1 2.1 BGA Quadrant Assignment...........................................................................2-1 2.2 Board Description .........................................................................................2-3 2.3 Routing Guidelines........................................................................................2-5 2.3.1 GTL+ Description.............................................................................2-6 2.3.2 GTL+ Layout Recommendations .....................................................2-6 2.3.3 Single Processor Design..................................................................2-6 2.3.3.1 Single Processor Network Topology and Conditions......2-6 2.3.3.2 Single Processor Recommended Trace Lengths ...........2-7 2.3.4 Dual Processor Systems..................................................................2-8 2.3.4.1 Dual Processor Network Topology and Conditions ........2-8 2.3.4.2 Dual Processor Recommended Trace Lengths..............2-8 2.3.5 Single Processor Systems—Single-End Termination (SET) ...........2-8 2.3.5.1 Set Network Topology and Conditions ...........................2-8 2.3.5.2 SET Trace Length Requirements ...................................2-9 2.3.6 Additional Guidelines .....................................................................2-10 2.3....
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