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Resumen del manual
The normalized values of these four analog levels are: +3, +1, –1 and –3. Each represents a symbol or quat. To provide precise adjustment of the transmitted power, the level of the DAC may be adjusted. The Transmitter Gain Register [tx_gain; 0x29] sets the level. During the manufacturing of the Bt8960, one source of variation in the transmitter levels is process variations. The Transmitter Calibration Register [tx_calibrate; 0x28] contains a read-only value which nulls this variation. The value of this register is determined for each Bt8960 device during production testing. Upon initialization, the Transmitter Gain Register should be loaded based on the Transmitter Calibration Register. If there are other sources of transmit power variation (e.g., a nonstandard hybrid or attenuative lightening protection), the transmitter gain must be adjusted to include these affects. 2.1.3 Pulse-Shaping Filter The pulse-shaping filter filters the quats output from the variable-gain DAC. This filter, when combined with other filtering in the signal path, produces a transmitted signal on the line that meets the power spectral density, transmitted power, and pulse-shaping requirements, as specified in the Electrical Specifications section of this datasheet. 2.1.4 Line Driver The line driver buffers the output of the pulse-shaping filter to drive diverse loads. The output of the line driver is differential. N8960DSB Bt8960 2.0 Functional Description Single-Chip 2B1Q Transceiver 2.2 Receive Section 2.2 Receive Section Like the transmit section, the receive section consists of both analog and digital circuitry. The VGA provides the interface to the analog signals received from the line and the hybrid. The Analog-to-Digital Converter (ADC) then digitizes the analog signal so it can be further processed in the digital signal Processing (DSP) section of the receiver. The receiver DSP section includes: front-end processing, echo cancellation, equalization, and symbol detection. 2.2.1 Variable Gain Amplifier The Variable Gain Amplifier (VGA) has two purposes. The first is to provide a dual-differential analog input so the pseudo-transmit signal created by the hybrid can be subtracted from the signal from the line transformer. This subtraction provides first-order echo cancellation, which results in a first-order approximation of the signal received from the line. Figure 2-1 illustrates the recommended suggested echo-cancellation circuit interconnections. All off-chip circuitry, including the hybrid and anti-alias filters, consists entirely of passive components. Further echo cancellation occurs in the receiver DSP. Figure 2-2. First-Order Echo Cancellation Using the Variable Gain Amplifier RXP RXN RXBP RXBN TXP TXN Line (Twisted Pair) To On-Chip CircuitryOff-Chip Circuitry Line Impedance Matching Gain[2:0] Anti-Alias Filter Hybrid – + Anti-alias Filter + – + – + – + – Line Driver Line Transformer + – Resistors ADC The second purpose of the VGA is to provide programmable gain of the received signal prior to passing it to the ADC. This reduces the resolution required for the ADC. There are six gain settings ranging from 0 dB to 15 dB. The gain is controlled via the gain[2:0] control bits in the ADC Control Register [adc_control; 0x21]. See the Registers section of this datasheet for a more detailed description of the gain[2:0] control bits. N8960DSB 2.0 Functional Description Bt8960 2.2 Receive Section Single-Chip 2B1Q Transceiver 2.2.2 Analog-to-Digital Converter The ADC provides 16 bits of resolution. The analog input from the variable gain amplifier is converted into digital data and output at the symbol rate. 2.2.3 Digital Signal Processor The Digital Signal Processor (DSP) includes five Least Mean Squared (LMS) filters: an Echo Canceller (EC), a Digital Automatic Gain Controller (DAGC), a Feed Forward Equalizer (FFE), an Error Predictor (EP), and a Decision Feedback Equalizer (DFE). These filters are used to equalize the received signal so that the symbols transmitted from the far-end can be reliably recovered. The DSP uses symbol rate sampling for all processing functions. Their interconnections and relationships to the digital front-end and the detector are illustrated in Figure 2-3. Figure 2-3. Receiver Digital Signal Processing Digital Front-End Channel Unit Interface Echo Canceller Transmit Symbol Equalizer DFE Detector LEC DAGC FFE NEC EP PKD Slicer–– –– – – N8960DSB Bt8960 2.0 Functional Description Single-Chip 2B1Q Transceiver 2.2 Receive Section 2.2.3.1 Digital Prior to the main signal processing, the input signal must be adjusted for any DC Front-End offset. The front-end module also monitors the input signal level, which includes measuring DC and AC input signal levels, detecting and counting overflows, and detecting alarms based on the far-end signal level. Figure 2-4 summarizes the features of the digital front-end module. Figure 2-4. Digital Front-End Block Diagram Echo-Free Signal from NEC DC Offset from MCI Accumu...
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