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Resumen del manual
011 Four-level scrambled ones. Transmits a scrambled, constant high logic level as a four- level (2B1Q) signal. Feedback polynomial determined by the htur_lfsr control bit. 100 Reserved. 101 Four-level scrambled data. Scrambles and transmits the four-level (2B1Q) sign and magnitude bits from the channel unit transmit interface. Feedback polynomial determined by the htur_lfsr control bit. 110 Two-level unscrambled data. Constantly forces the magnitude bit from the channel unit transmit interface to a logic zero and transmits the resulting two-level signal (as determined by the sign bit) without scrambling. Valid output levels limited to +3, –3. 111 Two-level scrambled ones. Transmits a scrambled, constant high-logic level as a two- level signal. Feedback polynomial determined by the htur_lfsr control bit. Scrambler is run at the symbol rate (half-bit rate) to produce the sign bit of the transmitted signal while the magnitude bit is sourced with a constant logic zero. Valid output levels limited to +3, –3. N8960DSB 3.0 Registers Bt8960 3.1 Conventions Single-Chip 2B1Q Transceiver 3.2.13 0x0C—Timer Restart Register (timer_restart) Independent read/write restart bits, one for each of the eight internal timers. Setting an individual bit causes the associated timer to be reloaded with the contents of its interval register. For the four symbol-rate timers (meter, snr, t3, t4), reloading will occur within one symbol period. For the four startup timers (sut1–4), reloading will occur within 1,024 symbol periods. Once reloaded, the restart bit is automatically cleared. If a restart bit is set and then cleared (by writing a logic zero) before the reload actually takes place, no timer reload will occur. Once reloaded, if enabled in the Timer Enable Register [timer_enable; 0x0D], the timer will begin counting down toward zero; otherwise, it will hold at the interval register value. 7 6 5 4 3 2 1 0 t4 t3 snr meter sut4 sut3 sut2 sut1 t4 General Purpose Timer 4 t3 General Purpose Timer 3 snr SNR Alarm Timer meter Meter Timer sut4 Startup Timer 4 sut3 Startup Timer 3 sut2 Startup Timer 2 sut1 Startup Timer 1 3.2.14 0x0D—Timer Enable Register (timer_enable) Independent read/write enable bits, one for each of the eight internal timers. When any individual bit is set, the corresponding timer is enabled for counting down from its current value toward zero. For the four symbol-rate timers (meter, snr, t3, t4), counting will begin within one symbol period. For the four startup timers (sut1-4), counting will begin within 1,024 symbol periods. When an enable bit is cleared, the timer is disabled from counting while it holds its current value. If an enable bit is set and then cleared before a count actually takes place, no timer countdown will occur. 7 6 5 4 3 2 1 0 t4 t3 snr meter sut4 sut3 sut2 sut1 t4 General Purpose Timer 4 t3 General Purpose Timer 3 snr SNR Alarm Timer meter Meter Timer sut4 Startup Timer 4 sut3 Startup Timer 3 sut2 Startup Timer 2 sut1 Startup Timer 1 N8960DSB Bt8960 3.0 Registers Single-Chip 2B1Q Transceiver 3.1 Conventions 3.2.15 0x0E—Timer Continuous Mode Register (timer_continuous) Independent read/write mode bits, one for each of the eight internal timers. When any individual bit is set, the corresponding timer is placed in the continuous count mode. While in this mode, after reaching the zero count, an enabled timer will reload the contents of its interval register and continue counting. When a mode bit is cleared, the timer is taken out of the continuous mode. While in this configuration, after reaching the zero count, an enabled timer will simply stop counting and remain at zero. 7 6 5 4 3 2 1 0 t4 t3 snr meter sut4 sut3 sut2 sut1 3.2.16 0x0F—Test Register (reserved2) A 1-byte read/write register used for device testing by Rockwell. This register is automatically initialized to 0x00 upon RST assertion and initial power application. This register must be initialized according to the device driver provided by Rockwell. 3.2.17 0x10, 0x11—Startup Timer 1 Interval Register (sut1_low, sut1_high) A 2-byte read/write register stores the countdown interval for Startup Timer 1 in unsigned binary format. Each increment represents 1,024 symbol periods. The contents of this register are automatically loaded into its associated timer after the timer’s timer_restart bit is set, or after it counts down to zero while in the continuous mode. 3.2.18 0x12, 0x13—Startup Timer 2 Interval Register (sut2_low, sut2_high) A 2-byte read/write register stores the countdown interval for Startup Timer 2 in unsigned binary format. Each increment represents 1,024 symbol periods. The contents of this register are automatically loaded into its associated timer after the timer’s timer_restart bit is set, or after it counts down to zero while in the continuous mode. 3.2.19 0x14, 0x15—Startup Timer 3 Interval Register (sut3_low, sut3_high) A 2-byte read/write register stores the countdown interval for Startup Timer 3 in unsigned binary fo...
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equipamiento barco - BT8960 (463.97 kb)