Device Comparison ¦ Meets Rambus® Extended Data Rate (XDR™) clocking requirements ¦ 25 ps typical cycle-to-cycle jitter . –135 dBc/Hz typical phase noise at 20 MHz offset ¦ 100 or 133 MHz differential clock input CY24271 CY24272 SDA hold time = 300 ns (SMBus compliant) SDA hold time = 0 ns (I2C compliant) RRC = 200. typical (Rambus standard drive) RRC = 295. minimum (Reduced output drive) ¦ 300–667 MHz high speed clock support ¦ Quad (open drain) differential output drivers ¦ Supports frequency

Notes 9. Jitter measured at crossing points and is the absolute value of the worst case deviation. 10. Measured at crossing points. 11. If input modulation is used; input modulation is allowed but not required. 12. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew that cannot exceed the skew generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%. 13. VOX

. BiCMOS technology Functional Description The CYV15G0404RB Independent Clock Quad HOTLink II™ Deserializing Reclocker is a point-to-point or point-to-multipoint communications building block enabling data transfer over a variety of high speed serial links including SMPTE 292 and SMPTE 259 video applications. It supports signaling rates in the range of 195 to 1500 Mbps for each serial link. The four channels are independent and can simultaneously operate at different rates. Each receive channel

BiCMOS technology Functional Description The CYV15G0104TRB Independent Clock HOTLink II™ Serializer and Reclocking Deserializer is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links including SMPTE 292M and SMPTE 259M video applications. It supports signaling rates in the range of 195 to 1500 Mbps per serial link. The transmit and receive channels are independent and can operate simultaneously at different rat

Absolute Maximum Ratings this circuit. For proper operation, VIN and VOUT should be constrained to the range, VSS < (VIN or VOUT) < VDD. All digital inputs are tied high or low internally. Refers to electrical specifications for operating supply range. Parameter Description Min. Max. Unit VDD Operating Voltage 3.0 6.0 VDC VIRvss Input, relative to VSS –0.3 VDD + 0.3 VDC VORvss Output, relative to VSS –0.3 VDD + 0.3 VDC TOP Temperature, Operating 0 +70 °C TST Temperature, Storage –65 +150 °C TJ T

*F Page 4 of 12 [+] Feedback FS781/82/84 Table 4. Modulation Rate Divider Ratios S1 S0 Input Frequency Range (MHz) Modulation Divider Number 0 0 6 to 16 120 0 1 16 to 32 240 1 0 32 to 66 480 1 1 66 to 82 720 SSCG Modulation Profile The digital control inputs S0 and S1 determine the modulation frequency of FS781/2/4 products. The input frequency is divided by a fixed number, depending on the operating range that is selected. The modulation frequency of the FS78x can be determined from Table 4. To

outputs • 6- to 82-MHz operating frequency range • Modulates external clocks including crystals, crystal oscillators, or ceramic resonators • Programmable modulation with simple R-C external loop filter (LF) • Center spread modulation • 3V-5V power supply • TTL-/CMOS-compatible outputs • Low short-term jitter • Low-power Dissipation — 3.3 VDC = 37 mW – typical — 5.0 VDC = 115 mW – typical • Available in 8-pin SOIC and TSSOP packages Applications • Desktop/notebook computers • Printers, copiers,

Aggregate throughput of up to 12 Gbits/second ¦ Second-generation HOTLink® technology ¦ Compliant to multiple standards . SMPTE-292M, SMPTE-259M, DVB-ASI, Fibre Channel, ESCON, and Gigabit Ethernet (IEEE802.3z) . 10 bit uncoded data or 8B/10B coded data ¦ Truly independent channels . Each channel is able to: • Perform reclocker function • Operate at a different signaling rate • Transport a different data format ¦ Internal phase-locked loops (PLLs) with no external PLL components ¦ Selectable dif

Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. 9. CMOS output buffer current and power dissipation specified at 50 MHz reference frequency. 10. Applies to REF and FB inputs only. 11. Test measurement levels for the CY7B9910 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B9920 are CMOS levels (VCC/2 to VCC/2). Test conditions assume signal transition times of 2ns or less and output loading as sho

The frequency of the REF and FB inputs are fNOM/2 or fNOM/4 when the part is configured for a frequency multiplication by using a divided output as the FB input. 3. When the FS pin is selected HIGH, the REF input must not transition upon power up until VCC has reached 4.3V. Document Number: 38-07138 Rev. *B Page 3 of 19 [+] Feedback CY7B991 CY7B992 Figure 1 shows the typical outputs with FB connected to a zero skew output.[4] Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output t –