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Resumen del manual
The bit which is set can be determined with the command: STATus:OPERation:CONDition? The data which is returned is the decimal weighted sum of the set bit. Since bit 8 is the only bit used by system instrument, 256 is returned if the bit is set. Bit 8 in the Condition register is cleared with the command: DIAGnostic:INTerrupt:RESPonse? When a condition monitored by the condition register occurs, a corresponding bit in the Operation Status Group Event register is automatically set. In order for this condition to generate a service request, the bit in the Event register must be unmasked using the Operation Status Group Enable register. This is done using the command: STATus:OPERation:ENABle < event> where event is the decimal weight of the bit to be unmasked. Since the system instrument only uses bit 8, the only useful value of event is 256. When bit 8 is set and is unmasked, it sets bit 7 in the Status Byte register in the Status Byte Group. Bits in the Operation Status Group Event register which are unmasked can be determined with the command: STATus:OPERation:ENABle? The command returns the decimal weighted sum of the unmasked bit(s). 6-8 Controlling Instruments Using GPIB Clearing the Operation Event Register Bits Using the Operation Status Group Registers Bits in the Operation Status Group Event register which are set can be determined with the command: STATus:OPERation:EVENt? This command returns the decimal weighted sum of the set bit(s). Bits in the Operation Status Group Event register are cleared with the command: STATus:OPERation:EVENt? or the bits can be cleared with the command: *CLS The Operation Status Group Enable register is cleared (all bits masked) by sending the command: STATus:OPERation:ENABle 0 The following example shows the sequence of commands used to setup and respond to an interrupt using the system instrument interrupt servicing routine. NOTE An interrupt handler must be assigned to handle the interrupt on the VXIbus backplane interrupt line specified. See "Interrupt Line Allocation" in Chapter 2 for more information. !Call computer subprogram Intr_resp when a service request ! is received due to an interrupt on a VXIbus backplane ! interrupt line. ON INTR 7 CALL Intr_resp ENABLE INTR 7;2 !Unmask bit 7 in the Status Byte register so that a service ! request (SRQ) will occur when an interrupt occurs. !Unmask bit 8 in the Operation Status Group Enable register !so that when the interrupt occurs it will set bit 7 in the !Status Byte register. OUTPUT 70900; "*SRE 128" OUTPUT 70900; "STAT:OPER:ENAB 256" !Set up interrupt line 5 and enable interrupt response data !to be generated. OUTPUT 70900; "DIAG:INT:SETUP5 ON" OUTPUT 70900; "DIAG:INT:ACT ON" . . (Program which executes until interrupt occurs) . !Computer service request routine which does an SPOLL !to determine the cause of the interrupt, then reads !(and clears) the Operation Event register to determine which !event occurred, and then reads the interrupt acknowledge ! response (which also clears condition register bit 8). Controlling Instruments Using GPIB 6-9 SUB Intr_resp B= SPOLL(70900) OUTPUT 70900; "STAT:OPER:EVEN?" ENTER 70900; E OUTPUT 70900; "DIAG:INTR:RESP?" ENTER 70900; R . . . SUBEND Clearing Status The *CLS command clears all status registers (Standard Event Status Register, Standard Operation Status Event Register, Questionable Data Status Event Register) and the error queue for an instrument. This clears the corresponding summary bits (bits 3, 5, & 7) and the instrument-specific bits (bits 0, 1, & 2) in the Status Byte Register. *CLS does not affect which bits are enabled to be reflected in the Status Byte Register or enabled to assert SRQ. Interrupting an External Computer When a bit in the status byte register is set and has been enabled to assert SRQ (*SRE command), the instrument sets the GPIB SRQ line true. Interrupts can be used to alert an external computer to suspend its present operation and find out what service the instrument requires. (Refer to your computer/language manuals for information on how to program the computer to respond to the interrupt.) To allow any of the status byte register bits to set the SRQ line true, you must first enable the bit(s) with the *SRE command. For example, suppose your application requires an interrupt whenever a message is available in the instrument’s output queue (status byte register bit 4). The decimal weight of this bit is 16. You can enable bit 4 to assert SRQ by sending: *SRE 16 NOTE You can determine which bits are enabled in the Status Register using *SRE?. This command returns the decimal weighted sum of all enabled bits. 6-10 Controlling Instruments Using GPIB Example: Interrupting when an Error Occurs This program shows how to interrupt an external computer whenever an error occurs for the instrument being programmed which, in this example, is a multimeter at secondary address 03. 10 OPTION BASE 1 !Array numbering starts with 1 20 ON INTR 7 CALL Errmsg !When SR...
Otros modelos de este manual:Equipo de red - 75000 SERIES B (3.89 mb)
Equipo de red - E1300B (3.89 mb)
Equipo de red - 75000 SERIES B (3.89 mb)