These bits always reflect the status of the processor, therefore they only have a reset value if the particular reset event affects the processor. For example, a PRESETDBGn event leaves these bits unchanged and a processor reset event such as nSYSPORESET sets DSCR[18] to a 0 and DSCR[1:0] to 10. To use the Debug Status and Control Register, read or write CP14 c1 with: MRC p14, 0, , c0, c1, 0 ; Read Debug Status and Control Register MCR p14, 0, , c0, c1, 0 ; Write Debug Status and Control

The region base address must always align to the region size. The MPU Region Base Address Registers are: • 32-bit read/write registers • accessible in Privileged mode only. Figure 4-34 shows the arrangement of bits in the registers. 31 5 04 Base address Reserved Figure 4-34 MPU Region Base Address Registers format Table 4-31 shows how the bit values correspond with the MPU Region Base Address Register functions. Table 4-31 MPU Region Base Address Registers bit functions Bits Field Function [31:5

All rights reserved. ARM DDI 0363E (ID013010) Cortex-R4 and Cortex-R4F Technical Reference Manual Copyright © 2009 ARM Limited. All rights reserved. Release Information The following changes have been made to this book. Change History Date Issue Confidentiality Change 15 May 2006 A Confidential First release for r0p1 22 October 2007 B Non-Confidential First release for r1p2 16 June 2008 C Non-Confidential Restricted Access First release for r1p3 11 September 2009 D Non-Confidential Second releas

All rights reserved. ARM DUI 0068B ARM Developer Suite Assembler Guide Copyright © 2000, 2001 ARM Limited. All rights reserved. Release Information The following changes have been made to this book. Change History Date Issue Change November 2000 A Release 1.1 November 2001 B Release 1.2 Proprietary Notice Words and logos marked with ® or ™ are registered trademarks or trademarks owned by ARM Limited. Other brands and names mentioned herein may be the trademarks of their respective owners. Neithe